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256m gddr sdram k4d553235f-gc - 1 - rev 1.1 (dec. 2004) 256mbit gddr sdram revision 1.1 december 2004 2m x 32bit x 4 banks graphic double data rate samsung electronics reserves the right to change products or specification without notice. (144-ball fbga) with bi-directional data strobe and dll synchronous dram
256m gddr sdram k4d553235f-gc - 2 - rev 1.1 (dec. 2004) revision history revision 1.1 (december 14, 2004) ? removed k4d553235f-gc20 from the specification. ? dualized the 400mhz part?s part number by its operating voltage. newly added -gj25 operating voltage is equal to 2.0v(typical) which is in mass production now. the 400mhz part with vdd & vddq= 1.8v (typical) which represented as -gc25 will be available by the 2nd quarter of ?05. revision 1.0 (september 21, 2004) ? defined dc specification revision 0.1 (june 16, 2004) - target spec ? defined target specification revision 0.0 (may 7, 2004) - target spec ? defined target specification
256m gddr sdram k4d553235f-gc - 3 - rev 1.1 (dec. 2004) the k4d553235f is 268,435,456 bits of hyper synchronous da ta rate dynamic ram organized as 4 x 2,097,152 words by 32 bits, fabricated with samsung ? s high performance cmos technology. sync hronous features with data strobe allow extremely high performance up to 3.6gb/ s/chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, programmable burst length and programma ble latencies allow the device to be useful for a variety of high performance memo ry system applications. ? 1.8v 0.1v power supply for device operation ? 1.8v 0.1v power supply for i/o interface ? sstl_18 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 4, 5 and 6 (clock) -. burst length (2, 4 and 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input general description features ? no wrtie-interrupted by read function ? 4 dqs?s ( 1dqs / byte ) ? data i/o transactions on both edges of data strobe ? dll aligns dq and dqs transitions with clock transition ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 32ms refresh period (4k cycle) ? 144-ball fbga ? maximum clock frequency up to 450mhz ? maximum data rate up to 900mbps/pin for 2m x 32bit x 4 bank ddr sdram 2m x 32bit x 4 banks graphic double data rate synchronous dram with bi-directional da ta strobe and dll ordering information * k4d553235f-vc is the lead free package part number. * the operating voltage of k4d5 53235f-gc22 is equal to 2.0v+ 0.1v * the opearting voltage of k4d553235f-gj25 is vdd/vddq=2.0v+ 0.1v. the 400mhz part with vdd&vddq=1.8v(typ) which represented as -gc25 will be available from 2q,'05 and it will fully cover -gj25 ?s operating voltage range as well. part no. max freq. max data rate interface package k4d553235f-gc22 450mhz 900mbps/pin sstl_18 144-ball fbga k4d553235f-gj25 400mhz 800mbps/pin k4d553235f-gc2a 350mhz 700mbps/pin k4d553235f-gc33 300mhz 600mbps/pin
256m gddr sdram k4d553235f-gc - 4 - rev 1.1 (dec. 2004) pin configuration (top view) pin description ck,ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 11 address input cs chip select dq 0 ~ dq 31 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq ? s dqs data strobe v ssq ground for dq ? s dm data mask nc no connection rfu reserved for future use mcl must connect low dqs0 vss rfu 1 thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vss vss vss vss vss vss vss vss vss rfu 2 a5 a6 dq4 dq6 dq7 dq17 dq19 dqs2 dq21 dq22 cas ras cs dm0 vddq dq5 vddq dq16 dq18 dm2 dq20 dq23 we nc nc nc vdd vddq vddq nc vddq vddq vdd nc ba0 ba1 a0 dq3 vddq dq31 dq1 a10 a2 a1 vdd vdd vdd dq2 vddq vdd a11 a3 a9 a4 dq0 vddq vdd dq29 dq30 dq28 vddq nc vss a7 vddq vddq nc vddq vddq vdd ck a8/ap dm3 vddq dq26 vddq dq15 dq13 dm1 dq11 dq9 nc ck cke dqs3 dq27 dq25 dq24 dq14 dq12 dqs1 dq10 dq8 nc vref 2345678910111213 b c d e f g h j k l m n note: 1. rfu1 is reserved for a12 2. rfu2 is reserved for ba2 3. vss thermal balls are optional mcl
256m gddr sdram k4d553235f-gc - 5 - rev 1.1 (dec. 2004) input/output functional description *1 : the timing reference point for the different ial clocking is the cross point of ck and ck. for any applications us ing the single ended clocking, apply v ref to ck pin. symbol type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on the rising edge of the clock except dq ? s and dm ? s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low indicates the power down mode or self refresh mode. cs input cs enables the command decoder when low and disabled the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras input latches row addresses on the positive going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the positive going edge of the ck with cas low. enables column access. we input enables write operation and row precharge. latches data in starting from cas , we active. dqs 0 ~ dqs 3 input/output data input and output are synchronized with both edge of dqs. dqs 0 for dq 0 ~ dq 7, dqs 1 for dq 8 ~ dq 15, dqs 2 for dq 16 ~ dq 23, dqs 3 for dq 24 ~ dq 31. dm 0 ~ dm 3 input data in mask. data in is masked by dm latency=0 when dm is high in burst write. dm 0 for dq 0 ~ dq 7, dm 1 for dq 8 ~ dq 15, dm 2 for dq 16 ~ dq 23, dm 3 for dq 24 ~ dq 31. dq 0 ~ dq 31 input/output data inputs/outputs are multiplexed on the same pins. ba 0 , ba 1 input selects which bank is to be active. a 0 ~ a 11 input row/column addresses are multiplexed on the same pins. row addresses : ra 0 ~ ra 11 , column addresses : ca 0 ~ ca 7 , ca 9 column address ca 8 is used for auto precharge. v dd /v ss power supply power and ground for the input buffers and core logic. v ddq /v ssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. nc/rfu no connection/ reserved for future use this pin is recommended to be left "no connection" on the device mcl must connect low must connect low
256m gddr sdram k4d553235f-gc - 6 - rev 1.1 (dec. 2004) block diagram (1mbit x 32i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 2mx32 2mx32 2mx32 2mx32 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck,ck addr lcke ck,ck cke cs ras cas we dmi ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck 64 64 32 32 lwe ldmi x32 dqi data strobe intput buffer dll (dqs0~dqs3)
256m gddr sdram k4d553235f-gc - 7 - rev 1.1 (dec. 2004) ? power-up sequence ddr sdrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply vdd before vddq . - apply vddq before vref & vtt 2. start clock and maintain stable condition for minimum 200us. 3. the minimum of 200us after stable power and clock(ck,ck ), apply nop and take cke to be high . 4. issue precharge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the additional 200 clock cycles are required to lock the dll. * 1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set command with a8 to low to initialize the mode register. *1 the additional 200cycles of clock input is required to lock the dll after ena bling dll. *2 sequence of 6&7 is regardless of the order functional description power up & initialization sequence command trp tmrd precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc emrs mrs tmrd. dll reset precharge all banks t rp inputs must be stable for 200us ~ ~ 200 clock min. tmrd ck,ck * when the operating frequency is change d, dll reset should be required again. after dll reset again, the mini mum 200 cycles of clock input is needed to lock the dll. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
256m gddr sdram k4d553235f-gc - 8 - rev 1.1 (dec. 2004) the mode register stores the data for controlling the vari ous operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and vari ous vendor specific options to make ddr sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for proper operation. t he mode register is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum two clock cycles are requested to complete the write o peration in the mode register. the mode register contents can be changed using the same command and clock cycle requirements du ring operation as long as all banks are in the idle state. the mode register is divided into various fi elds depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 7, a 8 , ba 0 and ba 1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addre ssing modes and cas latencies. mode register set(mrs) address bus mode register cas latency a 6 a 5 a 4 latency 000 reserved 001 reserved 010 reserved 011 reserved 100 4 101 5 110 6 111 reserved burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserved reserved 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved burst type a 3 type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. mrs cycle command *1 : mrs can be issued only at all banks precharge state. *2 : minimum t rp is required to issue mrs command. 0 ck, ck precharge nop nop mrs nop nop 2 01 6 12 10 11 any nop all banks command t rp t mrd =4 t ck ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu 0 rfu dll tm cas latency bt burst length ba 0 a n ~ a 0 0mrs 1emrs dll a 8 dll reset 0no 1yes test mode a 7 mode 0 normal 1test nop ~ ~ ~ ~ ~ ~ ~ ~
256m gddr sdram k4d553235f-gc - 9 - rev 1.1 (dec. 2004) the extended mode register stores the data for enabling or disabling dll and selecting output driver strength. the default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling dll. the extended mode register is written by assert- ing low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0, a2 ~ a5, a7 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. a1 and a6 are used for setting driver strength to norm al, weak or matched impedance. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle require ments during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. all the other address pins except a0,a1,a6 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0mrs 1emrs figure 7. extended mode register set extended mode register set(emrs) address bus extended *1 : rfu(reserved for future use) should st ay "0" during emrs cycle. a 6 a 1 output driver impedence control 00 full 100% 01 weak 60% 10 n/a do not use 11 matched 30% rfu 1 rfu d.i.c rfu d.i.c dll ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 mode register
256m gddr sdram k4d553235f-gc - 10 - rev 1.1 (dec. 2004) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. note : power & dc operating conditions(sstl in/out) recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 parameter symbol min typ max unit note device supply voltage v dd 1.7 1.8 1.9 v 1 output supply voltage v ddq 1.7 1.8 1.9 v 1 reference voltage v ref 0.49*v ddq - 0.51*v ddq v2 termination voltage vtt v ref -0.04 v ref v ref +0.04 v 3 input logic high voltage v ih(dc) v ref +0.15 - v ddq +0.30 v 4 input logic low voltage v il(dc) -0.30 - v ref -0.15 v 5 output logic high voltage v oh vtt+0.76 - - v i oh =-15.2ma, 7 output logic low voltage v ol - - vtt-0.76 v i ol =+15.2ma, 7 input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v dd supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 note :
256m gddr sdram k4d553235f-gc - 11 - rev 1.1 (dec. 2004) dc characteristics note : 1 refresh period is 32ms parameter symbol test condition version unit note -22 -25 -2a -33 operating current (one bank active) i cc1 burst lenth=2 t rc ac input operating conditions recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 parameter symbol min typ max unit note input high (logic 1) voltage ;dq v ih v ref +0.35 - - v input low (logic 0) voltage; dq v il --v ref -0.35 v clock input differential voltage; ck and ck v id 0.7 - v ddq +0.6 v 1 clock input crossing point voltage; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 2 1. v id is the magnitude of the diff erence between the input level on ck and the input level on ck 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same note :
256m gddr sdram k4d553235f-gc - 12 - rev 1.1 (dec. 2004) r t =50 ? ? decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other all v ss pins are connected in chip. all v ssq pins are connected in chip. note : ac operating test conditions (t a = 0 to 65 parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v1 ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il )v ref +0.4/v ref -0.4 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1 capacitance (t a = 25 parameter symbol min max unit input capacitance( ck, ck )c in1 1.0 5.0 pf input capacitance(a 0 ~a 11 , ba 0 ~ba 1 )c in2 1.0 4.0 pf input capacitance ( cke, cs , ras ,cas , we ) c in3 1.0 4.0 pf data & dqs input/output capacitance(dq 0 ~dq 31 )c out 1.0 6.5 pf input capacitance(dm0 ~ dm3) c in4 1.0 6.5 pf
256m gddr sdram k4d553235f-gc - 13 - rev 1.1 (dec. 2004) ac characteristics (i) parameter symbol -22 -25 -2a -33 unit note min max min max min max min max ck cycle time cl=3 tck - 5.0 - 10.0 - 10.0 - 10.0 ns cl=4 ---3.3ns cl=5 - 2.5 2.86 - ns cl=6 2.2 - - - ns ck high level width tch 0.45 0. 55 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqsck -0 .45 0.45 -0.45 0.45 -0.55 0.55 -0.55 0.55 ns output access time from ck tac -0.45 0.45 -0.45 0.45 -0.55 0.55 -0.55 0.55 ns data strobe edge to dout edge tdqsq - 0.28 - 0.28 - 0.35 - 0.35 ns 1 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1 .15 0.85 1.15 0.85 1.15 0.85 1.15 tck dqs-in setup time twpres 0 - 0 - 0 - 0 - ns dqs-in hold time twpreh 0.35 - 0.35 - 0.35 - 0.35 - tck dqs write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in high level width tdqsh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-in low level width tdqsl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck address and control input setup tis 0.55 - 0.6 - 0.8 - 0.8 - ns address and control input hold tih 0.55 - 0.6 - 0.8 - 0.8 - ns dq and dm setup time to dqs tds 0.27 - 0.3 - 0.35 - 0.35 - ns dq and dm hold time to dqs tdh 0.27 - 0.3 - 0.35 - 0.35 - ns clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin -ns1 data hold skew factor tqhs - 0.4 - 0.4 - 0.4 - 0.4 ns data output hold time from dqs tqh thp- tqhs - thp- tqhs - thp- tqhs - thp- tqhs -ns1 13467 tcl tck ck, ck dqs dq cs dm 25 tis tih 8 tds tdh 01 trpst trpre db0 db1 tdqss tdqsh tdqsl tch qa1 qa2 command reada writeb tdqsq t wpres t wpreh tdqsck tac simplified timi ng @ bl=2, cl=4
256m gddr sdram k4d553235f-gc - 14 - rev 1.1 (dec. 2004) note 1 : - the jedec ddr specification currently defines the output data va lid window(tdv) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used defini tion of tdv(=0.35tck) artificia lly penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applie d to the device is better than 45/55% - a new ac timing term, tqh which stands for data output hold time from dqs is difined to a ccount for clock duty cycle variation and replaces tdv - tqhmin = thp-x where . thp=minimum half clo ck period for any given cycle and is defined by clock high or cl ock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax tqh timing (cl4, bl2) 1 thp ck, ck dqs dq cs 25 01 command reada tqh qa0 tdqsq(max) tdqsq(max) 3 4 qa1 valid nop nop nop nop nop nop valid t is t is ck, ck cke command exit powr down mode enter power down mode (read or write operation must not be in progress) 3t ck power down timing
256m gddr sdram k4d553235f-gc - 15 - rev 1.1 (dec. 2004) ac characteristics (ii) note : 1. for normal write operation, even num bers of din are to be written inside dram 2. the number of clock of trp is restricted by the number of clock of tras and trp 3. the number of clock of twr_a is fixed. it c an?t be changed by tck. twr_a is related with cl. it is equal to cl+1 tck. 4. trcdwr is equal to trcdrd-2tck and the number of clock can not be lower than 2tck. 5. the minimum number of clock cycles is dete rmined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer unconditionally. parameter symbol -22 -25 -2a -33 unit note min max min max min max min max row cycle time trc 46.2 - 45 - 45.8 - 49.5 - ns 2,5 refresh row cycle time trfc 50.6 - 50 - 51.5 - 56.1 - ns 5 row active time tras 30.8 100k 28.6 100k 28.6 100k 33 100k ns 5 ras to cas delay for read trcdrd 15.4 - 15 - 16.5 - 16.5 - ns 5 ras to cas delay for write trcdwr 11 - 10 - 11.4 - 11.4 - ns 4,5 row precharge time trp 15.4 - 15 - 16.5 - 16.5 - ns 5 last data in to row precharge @normal precharge twr 15.4 - 15 - 16.5 - 16.5 - ns 1,5 last data in to row precharge @auto precharge twr_a 7 - 6 - 6 - 5 - tck 1,3 auto precharge write recovery + precharge tdal 30.8 - 30 - 33 - 33 - ns 3,5 row active to row active trrd 5 - 4 - 4 - 3 - tck last data in to read command tcdlr 2 - 2 - 2 - 2 - tck 1 col. address to col. address tccd 1 - 1 - 1 - 1 - tck mode register set cycle time tmrd 5 - 4 - 3 - 3 - tck exit self refresh to read command txsr 200 - 200 - 200 - 200 - tck power down exit time tpdex 3tck+ tis - 3tck+ tis - 3tck+ tis - 3tck+ tis -ns refresh interval time tref 7.8 - 7.8 - 7.8 - 7.8 - us
256m gddr sdram k4d553235f-gc - 16 - rev 1.1 (dec. 2004) ac characteristics (ii) k4d553235f-gc22 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 450mhz ( 2.2ns ) 6 21 23 14 7 5 7 5 14 tck 400mhz ( 2.5ns ) 5 18 20 12 6 4 6 4 12 tck k4d553235f-gj25 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 400mhz ( 2.5ns ) 5 18 20 12 6 4 6 4 12 tck k4d553235f-gc2a frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 350mhz ( 2.86ns ) 5 16 18 10 6 4 6 4 12 tck 300mhz ( 3.3ns ) 4 15 17 10 5 3 5 3 10 tck k4d553235f-gc33 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 300mhz ( 3.3ns ) 4 15 17 10 5 3 5 3 10 tck (unit : number of clock)
256m gddr sdram k4d553235f-gc - 17 - rev 1.1 (dec. 2004) 012345678 baa ra ra trcd activea activeb writea writeb 13 14 15 16 17 18 19 20 21 baa bab ca cb baa ca 9101112 prech baa 22 ra normal write burst (@ bl=4) multi bank interleaving write burst (@ bl=4) baa ra ra bab rb rb tras trc trp trrd command dqs dq we dm ck, ck a8/ap addr (a0~a7, ba[1:0] a9,a10) activea writea da0 da1 da2 da3 simplified timing(2) @ bl=4 db0 db1 db3 da0 da1 da2 da3 db2
256m gddr sdram k4d553235f-gc - 18 - rev 1.1 (dec. 2004) package dimensions (144-ball fbga) unit : mm 12.0 12.0 0.8 0.8 0.35 0.05 1.40 max 0.45 0.05 0.8x11=8.8 0.40 0.8x11=8.8 0.40 b c d e f g h j k l m n 13 12 11 10 9 8 7 6 5 4 3 2 a1 index mark a1 index mark 0.10 max

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